Journée Thématique "CAPITAL Workshop 2024: sCalable And PrecIse Timing AnaLysis for multicore platforms"

Dates : le 14 Juin 2024 de 9:00 à 15:10

Lieu : IRT Saint Exupéry, Toulouse, France

Organisateurs : Thomas CARLE, Eric JENN et Juan Maria RIVAS

Thématiques : Calcul embarqué haute performance et Systèmes Robustes Fiables et Sécurisés

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Keynote

Liliana Cucu-Grosjean, Senior researcher, INRIA Paris (Kopernic team), co-funder of Statinf:

Statistical, stochastic or probabilistic (worst-case) execution time – what impact on the multicore time composability?
Abstract: originally proposed within the real-time scheduling theory, the execution time of a program has received its stochastic definition in late ’90s before evolving to probabilistic worst-case execution time definition. Inspired by the static timing analysis, the probabilistic worst-case execution time estimation has been built on the composition of probability distribution at block level of programs, regardless of mathematical properties required to validate the correctness of obtained estimations. While initial research effort has been dedicated to model dependences between probability distributions of blocks for programs executed on single-core processors, statistical approaches have gained more interest for multicore processors as they allow building first theoretical bases for the validation of estimated worst-case execution times.

Invited speakers

Tomasz Kloda, LAAS-CNRS, Toulouse, France: Memory-centric scheduling for phased execution models on multi-core platforms

Federico Aromolo, Pisa University, Pisa, Italy: Timing Analysis of Parallel and Accelerated Software with Event-Driven Delay-Induced Tasks

Filippo Muzzini, UniMORE, Modena, Italy: Resource Contention Analysis in GPU-Accelerated Embedded Platforms

Frederic Bonamy, Thales Avionics, Toulouse, France: Multicore Challenges in Avionics Applications 

Program

9:00am: Keynote from Liliana Cucu-Grosjean (PDF)

10:00am: Break

10:15am: Filippo Muzzini: Resource Contention Analysis in GPU-Accelerated Embedded Platforms (PDF)

11:05am: Frederic Bonamy: Multicore Challenges in Avionics Applications (PDF)

12:00pm: Lunch break

1:30pm: Federico Aromolo: Timing Analysis of Parallel and Accelerated Software with Event-Driven Delay-Induced Tasks (PDF)

2:20pm: Tomasz Kloda: Memory-centric scheduling for phased execution models on multi-core platforms (PDF)

3:10pm: End of the workshop

General topic of the workshop

The design and the implementation of time-critical applications upon multi-core processors are considered. Multi-core processors have the potential to offer high computing power. Unfortunately, their extensive use of shared resources (e.g. caches, DRAM, buses, etc.) makes the design and the implementation difficult to predict — especially in situations where hard real-time constraints must be satisfied. Recent works show that an important challenge is to design a precise and scalable timing analysis. To address this challenge the research community considers closely both sides of the system: software and hardware. The aim of this co-design approach is therefore to guarantee scalability, precision and low complexity of the solution without compromising flexible efficient use of resources. The solution must be tailored for the target application and platform. In particular by identifying the shared resources (memory, bus, cache) and by reducing the complexity based on interference delay using, for instance, a tailored mapping/scheduling, bandwidth regulator. The solution must be also based on a good use of the hardware architecture (memory banks, cache, communication media) with techniques like physical/temporal partitioning to obtain a precise solution.