Type d'évènement : Evènements GDR
Date : du 1 Octobre au 28 Février 2026
Lieu :
Thales is a world leader for mission critical information systems for the security, defense, space and aerospace domains. It employs about 83,000 people in 68 countries. Following the success of the five previous national RISC-V student contests from 2020 to 2025, Thales, together with the GDR SOC² and the CNFM, are proud to announce the 6th edition of the contest (2025-2026).
This year’s contest will focus on architectural modifications of the CV32A6 RISC-V soft-core to accelerate a Fast Fourier Transform (FFT) algorithm processing 2n samples1. RISC-V is a recent open ISA that is gaining every day more attraction. From this ISA, ETH Zürich has designed a mid-range open-source application core named ARIANE. It has the capacity to execute rich operating systems and integrates an MMU function and several privilege levels. In 2019, the OpenHW Group (now OpenHW Foundation) was created with the ambition to design industrial-grade RISC-V processor core IPs. OpenHW has integrated the ARIANE core as its new 64-bit application core under the name CV64A6. Thales engineers have created a more compact 32-bit version from the original design, named CV32A6. CV32A6 and CV64A6 share the same source code and are together referred to as CVA6.
You are students and like new challenges. You are interested in electronics and computer architectures. You want to participate in the adventure of a renowned OpenHW processor core. Then join this contest and win up to € 5,000!